The present invention relates generally to non-volatile memory devices and related programming methods.
Non-volatile memory devices retain stored data when supplied power is interrupted. Flash type memory devices (hereafter “flash memory”) are one type of electrically erasable non-volatile memory commonly used in computers and memory cards.
Flash memory may be classified into NOR type flash and NAND type flash according to the logic gate connection between constituent memory cells and bit lines. NOR flash consumes greater current and has a less dense integration, but enjoys higher speed operation. NAND flash consumes less current and has greater integration density.
The memory cells in NAND flash are erased and programmed using the so-called Fowler-Nordheim tunneling phenomenon. Methods of erasing and programming NAND flash are disclosed, for example in U.S. Pat. Nos. 5,473,563 and 5,696,717, collective subject matter of which is hereby incorporated by reference.
NAND flash programming of selected memory cells may be had using an incremental step pulse programming (ISPP) method which accurately controls threshold voltage distributions for programmed memory cells. An exemplary circuit generating a program voltage for use during an ISPP method is disclosed, for example, in U.S. Pat. No. 5,642,309, the subject matter of which is hereby incorporated by reference.
However, conventional programming techniques suffer from a number of potential problems. For example, non-selected memory cells (i.e., memory cells not intended to be programmed during a current programming operation) may be adversely influenced by the programming operation directed to selected memory cells connected to the same word line. The program voltage is applied to the word line during the programming operation affects both selected and non-selected memory cells connected to the word line. Some non-selected memory cells connected to the word line, and especially those memory cells adjacent to a selected memory cell, may be programmed (or partially programmed) together with the selected memory cells. Instances where a non-selected memory cell connected to the selected word line (i.e., a word line receiving a program voltage during a program operation) are unintentionally programmed is commonly referred to as a “program disturb.”
A number of conventional approaches have been proposed to address the issue of program disturbs. One approach uses a program inhibit method characterized by a self-boosting scheme. See, for example, U.S. Pat. Nos. 5,677,873 and 5,991,202, the collective subject matter of which is hereby incorporated by reference.
In general, a program inhibit method using a self-boosting scheme cuts off a ground path by applying 0V to the gate of a ground selection transistor. This 0V signal is applied to the selection bit line while power supply voltages (e.g., 3.3V and 5V) are applied to a non-selected bit line as a program inhibit voltage. Simultaneously, by applying a power supply voltage to the gate of a string selection transistor, the source of a string selection transistor is charged from Vcc to Vth, where Vth is a threshold voltage of the string selection transistor, and the string selection transistor is substantially turned OFF. Then, a channel voltage of a program inhibited cell transistor is boosted by applying a program voltage Vpgm to a selected word line and applying a pass voltage Vpass to non-selected word lines. This prevents F-N tunneling between the floating gate and channel, such that the program inhibited cell transistor maintains an erase state.
Another program inhibit method using a local self-boosting scheme is presented in U.S. Pat. Nos. 5,715,194 and 6,061,270, the collective subject matter of which is hereby incorporated by reference.
According to the program inhibit method using the local self-boosting, a 0V signal is applied to the two (2) non-selected word lines adjacent to the selected word line. After a pass voltage Vpass (e.g., 10V) is applied to another non-selected word lines, the program voltage Vpgm is applied to the selected word line. Due to this bias scheme, the channel of a self-boosted cell transistor is limited to the selected word line. Moreover, the channel boosting voltage of the program inhibited cell transistor is further increased through the method using local self-boosting than the foregoing method using self-boosting. Therefore, F-N tunneling does not occur between the floating gate and channel of the program inhibited cell transistor, such that the program inhibited cell transistors maintains an erase state.